Reconfigurable GSM Digital up Converter for Multirate Systems

In this paper an efficient multiplier based approach is presented to implement digital up converter for Software Defined Radio based GSM applications. The proposed DUC design has been implemented by hybridizing the multiplier based and multiplier less techniques. The concept of polyphase decomposition technique has been used to map the design on multiplier based FPGA. The speed performance has been enhanced using MAC algorithm which is implemented using embedded multipliers of target FPGA. The polyphase decomposition technique has been supported by Park Mc Celellan algorithm to achieve optimal filter order which results in reduced hardware to provide area efficiency. The developed GSM digital up converter has been designed with Matlab, synthesized with Xilinx Synthesis Tool (XST), simulated with Modelsim and implemented on Virtex-II Pro based target FPGA device. The proposed design has shown an improvement of 16.4% in speed by consuming considerably less resources of target device to provide cost effective solution for wireless based multirate systems. Key-Words: DUC, FPGA, GSM, MAC, Multirate Systems, SDR